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1

Between-core vector overlapping for efficient core testing of system-on-chip LSI circuits

Tsuyoshi Shinogi, Yuki Yamada, Terumine Hayashi, Tomohiro Yoshikawa, Shinji Tsuruoka

Journal:

Electronics and Communications in Japan (Part II: Electronics))

Year:

2006

Language:

english

File:

PDF, 667 KB

english, 2006

2

4613970 Integrated circuit device and method of diagnosing the same

Ikuro Masuda, Hideo Maejima, Terumin Hayashi, Kazumi Hatayama

Journal:

Microelectronics Reliability

Year:

1987

Language:

english

File:

PDF, 88 KB

english, 1987

3

An enhanced fault model for high defect coverage

Junzhi Sang, Tsuyoshi Shinogi, Haruhiko Takase, Hidehiko Kita, Terumine Hayashi

Journal:

Systems and Computers in Japan

Year:

2001

Language:

english

File:

PDF, 263 KB

english, 2001

4

Sequential circuit test generation by real number simulation

Kazunori Hikone, Mitsuji Ikeda, Kazumi Hatayama, Terumine Hayashi

Journal:

Systems and Computers in Japan

Year:

1993

Language:

english

File:

PDF, 921 KB

english, 1993

5

On Test Data Compression Using Selective Don’t-Care Identification

Terumine Hayashi, Haruna Yoshioka, Tsuyoshi Shinogi, Hidehiko Kita, Haruhiko Takase

Journal:

Journal of Computer Science and Technology

Year:

2005

File:

PDF, 669 KB

2005

6

LSI module placement methods using neural computation networks

Hiroshi Date, Terumine Hayashi

Journal:

Electronics and Communications in Japan (Part III: Fundamental Electronic Science))

Year:

1991

Language:

english

File:

PDF, 544 KB

english, 1991

7

Test generation for stuck-on faults in pass-transistor logic SPL and implementation of DFT circuits

Tsuyoshi Shinogi, Terumine Hayashi, Kazuo Taki

Journal:

Systems and Computers in Japan

Year:

1999

Language:

english

File:

PDF, 8.56 MB

english, 1999

8

[IEEE 2007 International Joint Conference on Neural Networks - Orlando, FL, USA (2007.08.12-2007.08.17)] 2007 International Joint Conference on Neural Networks - Enhancing both generalization and fault tolerance of multilayer neural networks

Haruhiko, Takase, Masahiko, Mayumi, Hidehiko, Kita, Terumine, Hayashi

Year:

2007

Language:

english

File:

PDF, 190 KB

english, 2007

9

[IEEE Technology of Integrated Systems in Nanoscal Era (DTIS) - Cairo, Egypt (2009.04.6-2009.04.9)] 2009 4th International Conference on Design & Technology of Integrated Systems in Nanoscal Era - Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing

Shinogi, Tsuyoshi, Arakawa, Kanako, Hayashi, Terumine

Year:

2009

Language:

english

File:

PDF, 942 KB

english, 2009

10

[IEEE 2006 15th Asian Test Symposium - Fukuoka, Japan (2006.11.20-2006.11.20)] 2006 15th Asian Test Symposium - Low Power Oriented Test Modification and Compression Techniques for Scan Based Core Testing

Hayashi, Terumine, Ikeda, Naotsugu, Shinogi, Tsuyoshi, Takase, Haruhiko, Kita, Hidehiko

Year:

2006

Language:

english

File:

PDF, 145 KB

english, 2006

11

[IEEE 2008 IEEE International Joint Conference on Neural Networks (IJCNN 2008 - Hong Kong) - Hong Kong, China (2008.06.1-2008.06.8)] 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence) - Shape of error surfaces in SpikeProp

Fujita, Masaru, Takase, Haruhiko, Kita, Hidehiko, Hayashi, Terumine

Year:

2008

Language:

english

File:

PDF, 168 KB

english, 2008

12

[IEEE Technology of Integrated Systems in Nanoscale Era (DTIS) - Tozeur, Tunisia (2008.03.25-2008.03.27)] 2008 3rd International Conference on Design and Technology of Integrated Systems in Nanoscale Era - Peak power reduction method for Between-Core Vector Overlapping Testing

Wataru Suzuki,, Tsuyoshi Shinogi,, Terumine Hayashi,, Hiroharu Kawanaka,, Shinji Tsuruoka,

Year:

2008

Language:

english

File:

PDF, 1.93 MB

english, 2008

13

[IEEE 2009 International Joint Conference on Neural Networks (IJCNN 2009 - Atlanta) - Atlanta, Ga, USA (2009.06.14-2009.06.19)] 2009 International Joint Conference on Neural Networks - Obstacle to training SpikeProp networks — Cause of surges in training process —

Takase, Haruhiko, Fujita, Masaru, Kawanaka, Hiroharu, Tsuruoka, Shinji, Kita, Hidehiko, Hayashi, Terumine

Year:

2009

Language:

english

File:

PDF, 886 KB

english, 2009

14

Some Notes on Stability Problems of Probabilistic Automata

Hayashi., Terumine, Inagaki, Yasuyoshi, Fukumura†, Teruo

Journal:

Journal of Cybernetics

Year:

1971

Language:

english

File:

PDF, 795 KB

english, 1971

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